Modern bus systems for use in high-performance systems (e.g., a processor system) can operate at 400 MHz or more. Such high-speed systems can be susceptible to noise (e.g., supply noise due to switching of the circuits used to drive signals on the bus lines).
One solution is to use differential signaling schemes that help reduce sensitivity to common mode noise on the signal lines. However, differential signaling schemes have the disadvantage of doubling the number of signal lines and transceivers compared to single-ended schemes. Thus, for some applications, differential signaling may be undesirable. For example, some modern buses are 64-bits wide for data, thereby requiring 128 data signal lines. This relatively large number of data signal lines (and the associated transceivers) occupies valuable area on the chip(s) and wiring substrate (e.g., motherboard), which tends to increase the cost and complexity of the system.
On the other hand, if single-ended signal lines are used, in addition to the aforementioned noise sensitivity, the bus interfaces driving the signals on the signal lines can be “unbalanced”. That is, the number of logic low signals and logic high signals during a clock cycle may be different, resulting in a local net current flow in or out of a bus interface. This current flow can undesirably cause localized power supply noise (including simultaneously switching output (SSO) noise).